1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit and more specifically to a novel interconnection structure for an integrated circuit and its method of fabrication.
2. Discussion of the Related Art
Modern integrated circuits are made up of literally millions of active and passive devices such as transistors, capacitors, and resistors. These devices are initially isolated from one another but are later interconnected together to form functional circuits. The quality of the interconnection structure drastically affects the performance and reliability of the fabricated circuit. Interconnections are increasingly determining the limits of performance and density of modern ultra large scale integrated (ULSI) circuits.
FIG. 1a is a cross-sectional illustration of an interconnection structure which is presently used in the semiconductor industry. Formed in a silicon substrate or well 102 are active devices (not shown) such as transistors and capacitors. Interconnection lines 104 and 106, which are typically aluminum or aluminum alloys, are used to couple active devices into functional circuits. Metal interconnections 104 and 106 and substrate 102 are electrically isolated from one another by interlevel dielectric's (ILDs) 108 and 110, respectively. Electrical connections are made between metal interconnections 104 and 106 through the use of metal, typically tungsten, vias or plugs 112.
A serious reliability problem associated with interconnection structure of FIG. 1a and its method of fabrication is via delamination. Via delamination is a physical separation 114 between a via and the underlying metal interconnect as shown in FIG. 1b. Physical separation between a via connection and an underlying metal interconnection can cause open circuits to be formed resulting in complete failure of the device or circuit.
Although not entirely understood, via delamination is most likely the result of several factors including: high stresses in the ILD, interconnection, and via materials, contaminated metal interconnection/plug interfaces, and weak interconnection/ILD and interconnection/plug interfaces. During the lifetime of a semiconductor device, the device is subjected to substantial thermal cycling. For example, various temperature conditions are encountered throughout the entire manufacturing process and packaging of the device. Additionally, during device operation, large current densities flow through vias and interconnections causing temperature increases in high resistance areas such as the interface between vias and the underlying interconnection.
As a result of different thermal expansion coefficients of the metal interconnects, vias, and insulating layers, the via connections are subjected to large amounts of stress as the device is temperature cycled. Additionally, various residues consisting of fluorides and oxides, formed during the via etch process, are generally left at the interface prior to via metallization. These fluorides and oxides are generally brittle materials and when subjected to large amounts of thermal stress, crack and cause via delamination.
Thus, what is needed is a novel interconnection structure and method of fabrication which can resist via delamination.